參數(shù)資料
型號: SN75LVDS83BDGGR
廠商: Texas Instruments
文件頁數(shù): 7/30頁
文件大?。?/td> 0K
描述: IC FLATLINK XMITTER 56TSSOP
標(biāo)準(zhǔn)包裝: 1
系列: FlatLink™
類型: 發(fā)射器
驅(qū)動器/接收器數(shù): 5/0
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 907 (CN2011-ZH PDF)
其它名稱: 296-24529-6
SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011
APPLICATION INFORMATION
This section describes the power up sequence, provides information on device connectivity to various GPU and
LCD display panels, and offers a pcb routing example.
Power Up Sequence
The SN75LVDS83B does not require a specific power up sequence.
It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to
GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while
all other device blocks are still powered down.
It is also permitted to power up all 3.3V power domains while IOVCC is still powered down to GND. The device
will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true
input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the LVDS output
stage will turn on. The power consumption in this condition is significantly higher than standby mode, but still
lower than normal mode.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended:
Power up sequence (SN75LVDS83B SHTDN input initially low):
1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
2. Wait for additional 0-200ms to ensure display noise won’t occur.
3. Enable video source output; start sending black video data.
4. Toggle LVDS83B shutdown to SHTDN = VIH.
5. Send >1ms of black video data; this allows the LVDS83B to be phase locked, and the display to show black
data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (SN75LVDS83B SHTDN input initially high):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for >2 frame times.
3. Set SN75LVDS83B input SHTDN = GND; wait for 250ns.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.
Signal Connectivity
While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the
industry has aligned over the years on a certain data format (bit order). Figure 14 through Figure 17 show how
each signal should be connected from the graphic source through the SN75LVDS83B input, output and LVDS
LCD panel input. Detailed notes are provided with each figure.
Copyright 2009–2011, Texas Instruments Incorporated
15
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