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參數資料
| 型號： | SN751178NS |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ADSL Analog Front End 48-TQFP |
| 中文描述： | 雙差分驅動器和接收 |
| 文件頁數： | 10/11頁 |
| 文件大小： | 155K |
| 代理商： | SN751178NS |
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUARY 1990 – REVISED MAY 1999
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOL
VOH
tPHL
tPLH
Output
VOLTAGE WAVEFORMS
TEST CIRCUIT
50
Output
Input
0 V
3 V
Generator
(see Note B)
CL = 15 pF
(see Note A)
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR
≤
1 MHz, 50% duty cycle, ZO = 50
, tr
≤
6 ns, tf
≤
6 ns.
1.5 V
0 V
1.5 V
1.5 V
1.3 V
1.3 V
Figure 7. Receiver Propagation-Time Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMS
≈
1.3 V
0.5 V
tPHZ
3 V
0 V
VOH
Input
Output
0 V
3 V
VOL
S1 to –1.5 V
S2 Closed
S3 Open
VOL
1.5 V
≈
4.5 V
tPZL
3 V
1.5 V
0 V
Output
Input
tPZH
0 V
VOH
0 V
1.5 V
3 V
1.5 V
TEST CIRCUIT
1N916 or Equivalent
2 k
5 k
50
≈
1.3 V
tPLZ
S1 to –1.5 V
S2 Closed
S3 Closed
S1 to 1.5 V
S2 Closed
S3 Closed
Generator
(see Note B)
CL = 15 pF
(see Note A)
Input
Output
Output
Input
S1 to 1.5 V
S3 Closed
S2 Open
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR
≤
1 MHz, 50% duty cycle, ZO = 50
, tr
≤
6 ns, tf
≤
6 ns.
5 V
S3
1.5 V
–1.5 V
S1
S2
0.5 V
1.5 V
1.5 V
Figure 8. Receiver Output Enable- and Disable-Time Test Circuit and Voltage Waveforms
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