參數(shù)資料
型號(hào)： SN74SSTVF32852KR
廠商： TEXAS INSTRUMENTS INC
元件分類： 鎖存器
英文描述： SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114
封裝： PLASTIC, BGA-114
文件頁(yè)數(shù)： 1/13頁(yè)
文件大?。?/td> 442K
代理商： SN74SSTVF32852KR
SN74SSTVF32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES426A – FEBRUARY 2003 – REVISED MARCH 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus
Family
D Operates at 2.3 V to 2.7 V for PC1600,
PC2100, and PC2700; 2.5 V to 2.7 V for
PC3200
D Pinout and Functionality Compatible With
JEDEC Standard SSTV32852
D Pinout Optimizes 1U DDR DIMM Layout
D 600 ps Faster (Simultaneous Switching)
Than the JEDEC Standard SSTV32852 in
PC2700 DIMM Applications
D 1-to-2 Outputs Support Stacked DDR
DIMMs
D One Device Per DIMM Required
D Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
D Outputs Meet SSTL_2 Class I
Specifications
D Supports SSTL_2 Data Inputs
D Differential Clock (CLK and CLK) Inputs
D Supports LVCMOS Switching Levels on the
RESET Input
D RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits,
optimized for unterminated DIMM loads, and meet SSTL_2 Class I specifications.
The SN74SSTVF32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0
°C to 70°C
LFBGA – GKF
Tape and reel
SN74SSTVF32852KR
SVF852
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
Widebus is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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