參數(shù)資料
型號: SN74LVTH573RGYR
廠商: Texas Instruments
文件頁數(shù): 12/25頁
文件大?。?/td> 0K
描述: IC D-TYPE LATCH OCT 3-ST 20-VQFN
標準包裝: 1
系列: 74LVTH
邏輯類型: D 型透明鎖存器
電路: 8:8
輸出類型: 三態(tài)
電源電壓: 2.7 V ~ 3.6 V
獨立電路: 1
延遲時間 - 傳輸: 2.9ns
輸出電流高,低: 32mA,64mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應商設備封裝: 20-VQFN-EP(3.5x4.5)
包裝: 標準包裝
產(chǎn)品目錄頁面: 1001 (CN2011-ZH PDF)
其它名稱: 296-13988-6
SN54LVTH573, SN74LVTH573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS687H MAY 1997 REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
These octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
terminal assignments
1234
A
1D
OE
VCC
1Q
B
3D
3Q
2D
2Q
C
5D
4D
5Q
4Q
D
7D
7Q
6D
6Q
E
GND
8D
LE
8Q
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE
LE
D
OUTPUT
Q
L
H
L
HL
L
LX
Q0
H
X
Z
SN74LVTH573 . . . GQN OR ZQN PACKAGE
(TOP VIEW)
1
234
A
B
C
D
E
相關PDF資料
PDF描述
SN74LVTH573DBR IC OCTAL LATCH TRI-STATE 20-SSOP
1546105-7 TERM BLOCK PLUG 7POS VERT .200
284065-7 TERM BLOCK HEADER 7POS DL 5.08MM
284041-7 TERM BLOCK PLUG 7POS VERT 5.08MM
284040-7 TERM BLOCK PLUG 7POS VERT 5MM
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SN74LVTH574DBE4 功能描述:觸發(fā)器 3.3V ABT Octal Edge Trgerd DTyp FlipFlop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
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