參數(shù)資料
型號(hào): SN74LVT16244BGQLR
廠商: Texas Instruments
文件頁(yè)數(shù): 11/18頁(yè)
文件大?。?/td> 0K
描述: IC BUFF/DVR TRI-ST 16BIT 56BGA
標(biāo)準(zhǔn)包裝: 1
系列: 74LVT
邏輯類型: 緩沖器/線路驅(qū)動(dòng)器,非反相
元件數(shù): 4
每個(gè)元件的位元數(shù): 4
輸出電流高,低: 32mA,64mA
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFBGA
供應(yīng)商設(shè)備封裝: 56-BGA MICROSTAR JUNIOR(7.0x4.5)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 999 (CN2011-ZH PDF)
其它名稱: 296-8638-6
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
GQL OR ZQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3 4
6
5
K
GRD OR ZRD PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3
4
6
5
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS716E – MARCH 2000 – REVISED DECEMBER 2006
The 'LVT16244B devices are 16-bit buffers and line drivers designed for low-voltage (3.3-V) VCC operation, but
with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as four
4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical
active-low output-enable (OE) inputs.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
TERMINAL ASSIGNMENTS(1)
(56-Ball GQL/ZQL Package)
1
2
3
4
5
6
A
1OE
NC
2OE
B
1Y2
1Y1
GND
1A1
1A2
C
1Y4
1Y3
VCC
1A3
1A4
D
2Y2
2Y1
GND
2A1
2A2
E
2Y4
2Y3
2A3
2A4
F
3Y1
3Y2
3A2
3A1
G
3Y3
3Y4
GND
3A4
3A3
H
4Y1
4Y2
VCC
4A2
4A1
J
4Y3
4Y4
GND
4A4
4A3
xxxxxx
K
4OE
NC
3OE
xxxxxx
(1)
NC – No internal connection
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
1
2
3
4
5
6
A
1Y1
NC
1OE
2OE
NC
1A1
B
1Y3
1Y2
NC
1A2
1A3
C
2Y1
1Y4
VCC
1A4
2A1
D
2Y3
2Y2
GND
2A2
2A3
E
3Y1
2Y4
GND
2A4
3A1
F
3Y3
3Y2
GND
3A2
3A3
G
4Y1
3Y4
VCC
3A4
4A1
H
4Y3
4Y2
NC
4A2
4A3
J
4Y4
NC
4OE
3OE
NC
4A4
(1)
NC – No internal connection
2
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