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參數(shù)資料
| 型號(hào)： | SN74LVC573ADB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 中文描述： | 有三態(tài)輸出的8個(gè)透明D型鎖存器 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 127K |
| 代理商： | SN74LVC573ADB |
SN54LVC573A, SN74LVC573A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS300I – JANUARY 1993 – REVISED JUNE 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
CC
)
Power Off Disables Outputs, Permitting
Live Insertion
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and DIPs (J)
description
The SN54LVC573A octal transparent D-type latch
is designed for 2.7-V to 3.6-V V
CC
operation and
the SN74LVC573A octal transparent D-type latch
is designed for 1.65-V to 3.6-V V
CC
operation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Copyright
1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
SN54LVC573A . . . J OR W PACKAGE
SN74LVC573A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
SN54LVC573A . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
6Q
7Q
8Q
LE
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2
1
O
8
7
1
8
G
L
V
C
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| SN54LVC652AFK | Analog Multiplexers/Demultiplexers; Package: SOIC 16 LEAD; No of Pins: 16; Container: Rail; Qty per Container: 48 |
| SN74LVC652ADB | OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LVC573ADBR | 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LVC573ADBRE4 | 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LVC573ADBRG4 | 功能描述:閉鎖 Octal Transp DType Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LVC573ADGVR | 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LVC573ADGVRE4 | 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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