參數(shù)資料
型號: SN74LVC2G34DBVRE4
廠商: TEXAS INSTRUMENTS INC
元件分類: 門電路
英文描述: LVC/LCX/Z SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6
封裝: GREEN, PLASTIC, SOT-23, 6 PIN
文件頁數(shù): 1/17頁
文件大小: 796K
代理商: SN74LVC2G34DBVRE4
www.ti.com
FEATURES
3
2
4
6
1
1A
1Y
2Y
GND
2A
DBV PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
DCK PACKAGE
(TOP VIEW)
3
2
4
6
1
1A
1Y
2Y
GND
2A
3
2
4
6
1
1A
1Y
2Y
GND
2A
1A
2A
1Y
2Y
GND
DRL PACKAGE
(TOP VIEW)
See mechanical drawings for dimensions.
1
4
2
3
6
VCC
5
VCC
5
DESCRIPTION/ORDERING INFORMATION
DUAL BUFFER GATE
SCES359H – AUGUST 2001 – REVISED FEBRUARY 2007
Available in the Texas Instruments
Typical V
OHV (Output VOH Undershoot)
NanoFree Package
>2 V at VCC = 3.3 V, TA = 25°C
Supports 5-V V
CC Operation
I
off Supports Partial-Power-Down Mode
Operation
Inputs Accept Voltages to 5.5 V
Latch-Up Performance Exceeds 100 mA Per
Max t
pd of 4.1 ns at 3.3 V
JESD 78, Class II
Low Power Consumption, 10-A Max I
CC
ESD Protection Exceeds JESD 22
±24-mA Output Drive at 3.3 V
2000-V Human-Body Model (A114-A)
Typical V
OLP (Output Ground Bounce)
200-V Machine Model (A115-A)
<0.8 V at V
CC = 3.3 V, TA = 25°C
1000-V Charged-Device Model (C101)
This dual buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G34 performs the Boolean
function Y = A in positive logic.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoFree – WCSP (DSBGA)
Reel of 3000
SN74LVC2G34YZPR
_ _ _C9_
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74LVC2G34DBVR
SOT (SOT-23) – DBV
C34_
Reel of 250
SN74LVC2G34DBVT
–40
°C to 85°C
Reel of 3000
SN74LVC2G34DCKR
SOT (SC-70) – DCK
C9_
Reel of 250
SN74LVC2G34DCKT
SOT (SOT-533) – DRL
Reel of 4000
SN74LVC2G34DRLR
C9_
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 2001–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
相關PDF資料
PDF描述
SN74LVC2G34YZAR LVC/LCX/Z SERIES, DUAL 1-INPUT NON-INVERT GATE, BGA6
SN74LVC2G34YEPR LVC/LCX/Z SERIES, DUAL 1-INPUT NON-INVERT GATE, BGA6
SN74LVC2G74DCTRE4 LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
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