參數資料
型號: SN74LVC16373AGRDR
廠商: Texas Instruments, Inc.
英文描述: 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
中文描述: 16位透明D型鎖存器三態(tài)輸出
文件頁數: 2/14頁
文件大?。?/td> 331K
代理商: SN74LVC16373AGRDR
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
GQL OR ZQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
1
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4
5
6
SN74LVC16373A
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS755–DECEMBER 2003–REVISED MARCH 2005
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to V
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TERMINAL ASSIGNMENTS
(1)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
NC
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
NC
GND
V
CC
GND
NC
GND
V
CC
GND
NC
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
1LE
1D2
1D4
1D6
1D8
2D1
2D3
2D5
2D7
2LE
GND
V
CC
GND
NC
GND
V
CC
GND
NC
(1)
NC – No internal connection
2
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