參數(shù)資料
型號(hào)： SN74LV573ADB
廠商： Texas Instruments, Inc.
英文描述： OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
中文描述： 有三態(tài)輸出的8個(gè)透明D型鎖存器
文件頁(yè)數(shù)： 2/19頁(yè)
文件大小： 595K
代理商： SN74LV573ADB
SCLS411I APRIL 1998 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The ’LV573A devices are octal transparent D-type latches designed for 2-V to 5.5-V V
CC
operation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
terminal assignments
1
2
3
4
A
1D
OE
VCC
2D
1Q
B
3D
3Q
2Q
C
5D
4D
5Q
4Q
D
7D
7Q
6D
6Q
E
GND
8D
LE
8Q
FUNCTION TABLE
(each latch)
INPUTS
LE
OUTPUT
Q
OE
D
L
H
H
H
L
H
L
L
L
L
X
Q0
Z
H
X
X
GQN PACKAGE
(TOP VIEW)
1
2
3
4
A
B
C
D
E
相關(guān)PDF資料
PDF描述
SN54LV573A Octal 3-State Non-Inverting Transparent Latch; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Rail; Qty per Container: 75
SN54LV573AFK Octal 3-State Non-Inverting Transparent Latch; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2500
SN54LV573AJ Octal 3-State Non-Inverting Transparent Latch; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2500
SN54LV573AW Octal 3-State Non-Inverting Transparent Latch; Package: SOIC-20 WB; No of Pins: 20; Container: Rail; Qty per Container: 38
SN74LV573ADGV Bipolar Power TO220 PNP 1A 375V; Package: TO-220 3 LEAD STANDARD; No of Pins: 3; Container: Rail; Qty per Container: 50
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74LV573ADBR 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
SN74LV573ADBRE4 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
SN74LV573ADBRG4 功能描述:閉鎖 Octal Transp DType 閉鎖 RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
SN74LV573ADGVR 功能描述:閉鎖 Octal Transp DType 閉鎖 RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
SN74LV573ADGVRE4 功能描述:閉鎖 Octal Transp DType 閉鎖 RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
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