參數(shù)資料
型號(hào)： SN74LV373ANS
廠商： Texas Instruments, Inc.
英文描述： Shaft; Style: 1 - light; Applicable Model: LCE / LCE-U
中文描述： 八路透明D類鎖存器具有三態(tài)輸出
文件頁數(shù)： 1/8頁
文件大小： 153K
代理商： SN74LV373ANS
SN54LV373A, SN74LV373A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS407A – APRIL 1998 – REVISED JUNE 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
, T
A
= 25
°
C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic
Small-Outline (DW, NS), Shrink
Small-Outline (DB), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Packages, Chip
Carriers (FK), and DIPs (J)
description
The ’LV373A devices are octal transparent D-type
latches designed for 2-V to 5.5-V V
CC
operation.
While the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LV373A is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74LV373A is characterized for operation from –40
°
C to 85
°
C.
Copyright
1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1
1
O
5
5
V
8
4
G
L
SN54LV373A . . . FK PACKAGE
(TOP VIEW)
SN54LV373A . . . J OR W PACKAGE
SN74LV373A . . . DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
相關(guān)PDF資料
PDF描述
SN54LV373AW Octal D-Type Flip-Flop; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Rail; Qty per Container: 75
SN54LV373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LV374ADGVR OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SN74LV374AGQNR Insulation Displacement (IDC) Connector; No. of Contacts:40; Contact Termination:IDC; Gender:Female; Contact Plating:Nickel; Pitch Spacing:0.05" RoHS Compliant: Yes
SN74LV374ARGYR OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74LV373ANSR 功能描述:閉鎖 Octal Transp DType Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
SN74LV373ANSRE4 功能描述:閉鎖 Octal Transp DType Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
SN74LV373ANSRG4 功能描述:閉鎖 Octal Transp DType Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
SN74LV373APW 功能描述:閉鎖 Octal Transp DType Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
SN74LV373APWE4 功能描述:閉鎖 Octal Transp DType Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
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