參數(shù)資料
型號(hào): SN74LV367ADGV
廠商: Texas Instruments, Inc.
英文描述: Bipolar Power DPAK NPN 0.5A 300V; Package: DPAK 4 LEAD Single Gauge Surface Mount; No of Pins: 4; Container: Rail; Qty per Container: 75
中文描述: 六角緩沖器和線路驅(qū)動(dòng)器,三態(tài)輸出
文件頁(yè)數(shù): 1/8頁(yè)
文件大小: 127K
代理商: SN74LV367ADGV
SN54LV367A, SN74LV367A
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD-22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
The ’LV367A devices are hex buffers and line
drivers designed for 2-V to 5.5-V V
CC
operation.
These devices are designed specifically to
improve both the performance and density of
3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters.
The ’LV367A devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE
and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When
OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LV367A is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74LV367A is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each buffer/driver)
INPUTS
OE
OUTPUT
Y
A
L
H
H
L
L
L
H
X
Z
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2A2
2Y2
NC
2A1
2Y1
1Y1
1A2
NC
1Y2
1A3
1
1
N
1
1
V
2
1
G
N
SN54LV367A . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OE
1A1
1Y1
1A2
1Y2
1A3
1Y3
GND
V
CC
2OE
2A2
2Y2
2A1
2Y1
1A4
1Y4
SN54LV367A . . . J OR W PACKAGE
SN74LV367A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright
1999, Texas Instruments Incorporated
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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