
SN74LV123AEP
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR
WITH SCHMITT TRIGGER INPUTS
SCLS498A MAY 2003 REVISED MAY 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Controlled Baseline
One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
40
°C to 105°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Supports Mixed-Mode Voltage Operation on
All Ports
D Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
D Ioff Supports Partial-Power-Down Mode
Operation
D Retriggerable for Very Long Output Pulses,
Up To 100% Duty Cycle
D Overriding Clear Terminates Output Pulse
D Glitch-Free Power-Up Reset on Outputs
D ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
description/ordering information
The SN74LV123A is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCC operation.
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method,
the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes
low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor
connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable
resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
40
°C to 105°C
TSSOP PW
Tape and reel
SN74LV123ATPWREP
L123AEP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1B
1CLR
1Q
2Q
2Cext
2Rext/Cext
GND
VCC
1Rext/Cext
1Cext
1Q
2Q
2CLR
2B
2A
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.