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參數(shù)資料
| 型號： | SN74LV10ADBR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TRIPLE 3-INPUT POSITIVE-NAND GATE |
| 中文描述： | 三重3輸入陽性與非門 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 332K |
| 代理商： | SN74LV10ADBR |
SCES338E SEPTEMBER 2000 REVISED APRIL 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2-V to 5.5-V V
CC
Operation
Max t
pd
of 7 ns at 5 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
>2.3 V at V
CC
= 3.3 V, T
A
= 25
°
C
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
description/ordering information
These triple 3-input positive-NAND gates are
designed for 2-V to 5.5-V V
CC
operation.
The ’LV10A devices perform the Boolean function
Y = A
B
C or Y = A + B + C in positive logic.
These
partial-power-down applications using I
off
. The I
off
circuitry
disables
the
damaging current backflow through the devices
when they are powered down.
devices
are
fully
specified
for
outputs,
preventing
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC D
Tube of 50
SN74LV10AD
LV10A
Reel of 2500
SN74LV10ADR
SOP NS
Reel of 2000
SN74LV10ANSR
74LV10A
40
°
C to 85
°
C
SSOP DB
Reel of 2000
SN74LV10ADBR
LV10A
Tube of 90
SN74LV10APW
TSSOP PW
Reel of 2000
SN74LV10APWR
LV10A
Reel of 250
SN74LV10APWT
TVSOP DGV
Reel of 2000
SN74LV10ADGVR
LV10A
CDIP J
Tube of 25
SNJ54LV10AJ
SNJ54LV10AJ
55 C to 125 C
CFP W
LCCC FK
Tube of 150
Tube of 55
SNJ54LV10AW
SNJ54LV10AFK
SNJ54LV10AW
SNJ54LV10AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2005, Texas Instruments Incorporated
SN54LV10A . . . FK PACKAGE
(TOP VIEW)
SN54LV10A . . . J OR W PACKAGE
SN74LV10A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
2A
2B
2C
2Y
GND
V
CC
1C
1Y
3C
3B
3A
3Y
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
1Y
NC
3C
NC
3B
2A
NC
2B
NC
2C
1
1
N
3
3
V
1
2
G
N
NC No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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相關PDF資料 |
PDF描述 |
|---|---|
| SN74LV10APWT | TRIPLE 3-INPUT POSITIVE-NAND GATE |
| SNJ54LV10AFK | TRIPLE 3-INPUT POSITIVE-NAND GATE |
| SNJ54LV10AJ | TRIPLE 3-INPUT POSITIVE-NAND GATE |
| SNJ54LV10AW | TRIPLE 3-INPUT POSITIVE-NAND GATE |
| SN54LV10A | TRIPLE 3-INPUT POSITIVE-NAND GATE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LV10ADBRE4 | 功能描述:邏輯門 Triple 3-Input Positive-NAND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| SN74LV10ADBRG4 | 功能描述:邏輯門 Triple 3 Input Pos NAND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| SN74LV10ADE4 | 功能描述:邏輯門 Triple 3-Input Positive-NAND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| SN74LV10ADG4 | 功能描述:邏輯門 Triple 3 Input Pos NAND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| SN74LV10ADGVR | 功能描述:邏輯門 Triple 3-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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