- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373476 > SN74GTLPH32945_07 (Texas Instruments, Inc.) 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER PDF資料下載
參數(shù)資料
| 型號(hào)： | SN74GTLPH32945_07 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER |
| 中文描述： | 32位LVTTL至GTLP總線收發(fā)器 |
| 文件頁(yè)數(shù)： | 1/17頁(yè) |
| 文件大?。?/td> | 421K |
| 代理商： | SN74GTLPH32945_07 |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)
www.ti.com
FEATURES
Member of the Texas Instruments Widebus+
Family
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
DESCRIPTION/ORDERING INFORMATION
The SN74GTLPH32945 is a medium-drive, 32-bit bus transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It is partitioned as four 8-bit transceivers. The device provides a
high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal
levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result
of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC circuitry,
and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been
designed and tested using several backplane models. The medium drive allows incident-wave switching in
heavily loaded backplanes with equivalent load impedance down to 19
.
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLPH32945 is given only at the preferred higher noise margin GTLP, but the
user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V and
V
REF
= 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
REF
is the B-port differential input
reference voltage.
SN74GTLPH32945
32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES293C–OCTOBER 1999–REVISED JUNE 2005
LVTTL Outputs (–24 mA/24 mA)
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
I
off
, Power-Up 3-State, and BIAS V
CC
Support
Live Insertion
Bus Hold on A-Port Data Inputs
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal
integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMMER
SN74GTLPH32945KR
TOP-SIDE MARKING
GM45
–40
°
C to 85
°
C
LFBGA – GKE
Tape and reel
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, TI-OPC, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 1999–2005, Texas Instruments Incorporated
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74H103N | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR |
| SN74H103 | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR |
| SN74H103J | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR |
| SN74HC02DB | QUADRUPLE 2-INPUT POSITIVE-NOR GATES |
| SN54HC02FK | QUADRUPLE 2-INPUT POSITIVE-NOR GATES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74GTLPH32945KR | 功能描述:轉(zhuǎn)換 - 電壓電平 32bit LVTTL-GTLP RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLPH32945ZKER | 功能描述:轉(zhuǎn)換 - 電壓電平 32B LVTTL to GTLPBus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74H00J | 制造商: 功能描述: 制造商:undefined 功能描述: |
| SN74H00N | 制造商:Texas Instruments 功能描述: |
| SN74H01N | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。