參數(shù)資料
型號(hào)： SN74GTLP22034GQLR
廠商： Texas Instruments, Inc.
元件分類(lèi)： 通用總線功能
英文描述： 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
中文描述： 8位LVTTL至GTLP可調(diào)EDGE的速率收發(fā)器劈開(kāi)登記LVTTL港口及反饋路徑
文件頁(yè)數(shù)： 8/20頁(yè)
文件大?。?/td> 366K
代理商： SN74GTLP22034GQLR
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C
–
JUNE 2001
–
REVISED SEPTEMBER 2001
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Notes 4 through 7)
MIN
NOM
MAX
UNIT
VCC,
BIAS VCC
Supply voltage
3.15
3.3
3.45
V
VTT
Termination voltage
GTL
1.14
1.2
1.26
V
GTLP
1.35
1.5
1.65
VREF
Reference voltage
GTL
0.74
0.8
0.87
V
GTLP
0.87
1
1.1
VI
Input voltage
B port
VTT
5.5
V
Except B port and VREF
B port
VCC
VIH
High level input voltage
High-level input voltage
VREF+0.05
V
Except B port
2
VIL
Low level input voltage
Low-level input voltage
B port
VREF
–
0.05
0.8
V
Except B port
IIK
IOH
Input clamp current
–
18
mA
High-level output current
AO
–
12
mA
IOL
Low level output current
Low-level output current
AO
12
mA
B port
100
t/
v
t/
VCC
TA
NOTES:
Input transition rise or fall rate
Outputs enabled
10
ns/V
μ
s/V
°
C
Power-up ramp rate
20
Operating free-air temperature
–
40
85
4. All unused control and B-port inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI
application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V ast, because the BIAS VCC precharge circuitry s disabled when any VCC pin s connected. The control and VREF nputs
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable but, generally, GND is connected first.
6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction
and is activated when VTT
>
0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to
minimize current drain.
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