參數(shù)資料
型號: SN74FB2033H
廠商: Texas Instruments, Inc.
英文描述: 8-BIT TTL/BTL REGISTERED TRANSCEIVER
中文描述: 8位TTL /橋接注冊收發(fā)器
文件頁數(shù): 2/10頁
文件大小: 151K
代理商: SN74FB2033H
SN74FB2033H
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472B – MAY 1994 – REVISED JUNE 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the
LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the
output of the selected A-to-B logic element (prior to inversion) is the B-to-A input.
The AO port-enable/-disable control is provided by OEA. When OEA is low or when V
CC
is less than 2.5 V, the
AO port is in the high-impedance state. When OEA is high, the AO port is active (high or low logic levels).
The B port is controlled by OEB and OEB. If OEB is low, or OEB is high, or when V
CC
is less than 2.5 V, the B port
is inactive. If OEB is high and OEB is low, the B port is active.
BG V
CC
and BG GND are the bias-generator reference inputs.
The A-to-B and B-to-A logic elements are active regardless of the state of their associated outputs. The logic
elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated
outputs are in the high-impedance (AO port) or inactive (B port) states.
Output clamps are provided on the BTL outputs to reduce switching noise. One clamp reduces inductive ringing
effects on V
OH
during a low-to-high transition. The other clamps out ringing below the BTL V
OL
voltage of 0.75 V.
Both of these clamps are active only during AC switching and do not affect the BTL outputs during steady-state
conditions.
BIAS V
CC
establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when V
CC
is not connected.
The SN74FB2033H is characterized for operation from 0
°
C to 70
°
C.
Function Tables
FUNCTION TABLE
INPUTS
OMODE0
X
FUNCTION/MODE
OEA
L
OEB
L
OEB
X
OMODE1
X
IMODE1
X
IMODE0
X
LOOPBACK
X
Isolation
L
X
H
X
X
X
X
X
X
H
L
L
L
X
X
X
AI to B, buffer mode
X
H
L
L
H
X
X
X
AI to B, flip-flop mode
X
H
L
H
X
X
X
X
AI to B, latch mode
H
L
X
X
X
L
L
L
B to AO buffer mode
B to AO, buffer mode
H
X
H
X
X
L
L
L
H
L
X
X
X
L
H
L
B to AO flip flop mode
B to AO, flip-flop mode
H
X
H
X
X
L
H
L
H
L
X
X
X
H
X
L
B to AO latch mode
B to AO, latch mode
H
X
H
X
X
H
X
L
H
L
X
X
X
L
L
H
AI to AO buffer mode
AI to AO, buffer mode
H
X
H
X
X
L
L
H
H
L
X
X
X
L
H
H
AI to AO flip flop mode
AI to AO, flip-flop mode
H
X
H
X
X
L
H
H
H
L
X
X
X
H
X
H
AI to AO latch mode
AI to AO, latch mode
H
X
H
X
X
H
X
H
H
H
L
X
X
X
X
L
AI to B, B to AO
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