參數(shù)資料
型號： SN74F174
廠商： Texas Instruments, Inc.
英文描述： HEX D-TYPE FLIP-FLOP WITH CLEAR
中文描述： 六角D型倒裝，沒有明確的浮點運算
文件頁數(shù)： 3/5頁
文件大?。?/td> 69K
代理商： SN74F174
SN74F174A
HEX D-TYPE FLIP-FLOP
WITH CLEAR
SDFS029B – D2932, MARCH 1987 – REVISED OCTOBER 1993
2–3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4.75 V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
II = – 18 mA
IOH = – 1 mA
IOH = – 1 mA
IOL = 20 mA
VI = 7 V
VI = 2.7 V
VI = 0.5 V
VO = 0
See Note 2
– 1.2
V
VOH
2.5
3.4
V
2.7
VOL
II
IIH
IIL
IOS
ICCH
ICCL
0.3
0.5
V
0.1
mA
μ
A
mA
20
– 0.6
– 60
– 150
mA
30
45
mA
See Note 3
39
55
mA
All typical values are at VCC = 5 V, TA = 25
°
C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTES:
2. ICCH is measured with all outputs open, all data inputs and enable input at 4.5 V, and the clock input at 4.5 V after being momentarily
grounded.
3. ICCL is measured with all outputs open, all data inputs and enable input at 0 V, and the clock input at 4.5 V after being momentarily
grounded.
timing requirements
VCC = 5 V,
TA = 25
°
C
MIN
VCC = 4.5 V to 5.5 V,
TA = MIN to MAX§
MIN
UNIT
MAX
MAX
fclock
Clock frequency
0
100
0
80
MHz
CLK high
4
4
tw
Pulse duration
CLK low
6
6
ns
CLR low
5
5
tsu
Setup time before CLK
↑
Data high or low
4.5
4.5
ns
CLR high
5
5
th
Hold time after CLK
↑
Data high or low
0.5
1
ns
§For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Inactive-state setup time is also referred to as recovery time.
switching characteristics (see Note 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500
,
TA = 25
°
C
MIN
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX§
MIN
UNIT
TYP
MAX
MAX
fmax
tPLH
tPHL
tPHL
100
140
80
MHz
CLK
Any Q
2.7
4.5
8
2.7
9
ns
3.4
4.2
10
3.3
11
CLR
Any Q
4.2
6.3
14
4.2
15
ns
NOTE 4: Load circuits and waveforms are shown in Section 1.
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