參數(shù)資料
型號(hào): SN74CBT3126DGV
廠商: Texas Instruments, Inc.
英文描述: QUADRUPLE FET BUS SWITCH
中文描述: 四路場(chǎng)效應(yīng)管總線開(kāi)關(guān)
文件頁(yè)數(shù): 3/4頁(yè)
文件大?。?/td> 63K
代理商: SN74CBT3126DGV
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020E – MAY 1995 – REVISED MAY 1998
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4 V
VCC = 5 V
±
0.5 V
UNIT
MIN
MAX
MIN
MAX
tpd
ten
tdis
A or B
B or A
0.35
0.25
ns
OE
A or B
5.4
1.6
5.1
ns
OE
A or B
5
1
4.5
ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
tPLH
tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
1.5 V
1.5 V
3 V
0 V
1.5 V
1.5 V
VOH
VOL
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
0 V
Input
3 V
3.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH andtPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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