參數(shù)資料
型號(hào): SN74AUP1G34DRLR-PDSO-N5
廠商: Texas Instruments, Inc.
英文描述: LOW-POWER SINLE BUFFER GATE
中文描述: 低功耗新樂(lè)緩沖門
文件頁(yè)數(shù): 2/11頁(yè)
文件大小: 225K
代理商: SN74AUP1G34DRLR-PDSO-N5
SCES590 JULY 2004
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
NanoStar
and NanoFree
package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
NanoStar
WCSP (DSBGA)
0.23-mm Large Bump YEP
Reel of 3000
SN74AUP1G06YEPR
_ _ _HT_
NanoFree
WCSP (DSBGA)
0.23-mm Large Bump YZP (Pb-free)
SN74AUP1G06YZPR
40
°
C to 85
°
C
SOT (SOT-23) DBV
Reel of 3000
SN74AUP1G06DBVR
H06_
Reel of 250
Reel of 3000
SN74AUP1G06DBVT
SN74AUP1G06DCKR
SOT (SC-70) DCK
HT_
Reel of 250
SN74AUP1G06DCKT
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb,
= Pb-free).
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram (positive logic)
A
Y
2
4
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