參數(shù)資料
型號: SN74AUP1G34DBVR-PDSO-G5
廠商: Texas Instruments, Inc.
英文描述: LOW-POWER SINLE BUFFER GATE
中文描述: 低功耗新樂緩沖門
文件頁數(shù): 3/11頁
文件大?。?/td> 225K
代理商: SN74AUP1G34DBVR-PDSO-G5
SCES590 JULY 2004
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
Input voltage range, V
I
(see Note 1)
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range in the high or low state, V
O
(see Note 1)
Input clamp current, I
IK
(V
I
< 0)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θ
JA
(see Note 2): DBV package
DCK package
YEP/YZP package
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
0.5 V to 4.6 V
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.5 V to 4.6 V
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . .
50 mA
50 mA
±
20 mA
±
50 mA
206
°
C/W
252
°
C/W
132
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . .
65
°
C to 150
°
C
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
VCC
Supply voltage
0.8
3.6
V
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC
VIH
High-level input voltage
0.65
×
VCC
1.6
V
2
0
VIL
Low-level input voltage
0.35
×
VCC
0.7
V
0.9
VI
VO
Input voltage
0
3.6
V
Output voltage
0
3.6
V
μ
A
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
VCC = 0.8 V to 3.6 V
20
1.1
Low-level output current
1.7
IOL
1.9
mA
3.1
4
t/
v
TA
Defined by the signal integrity requirements and design-goal priorities
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Input transition rise or fall rate
200
ns/V
°
C
Operating free-air temperature
40
85
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