參數(shù)資料
型號(hào): SN74AUCH240
廠商: Texas Instruments, Inc.
英文描述: Octal Buffer/Driver with 3-State Outputs
中文描述: 具有三態(tài)輸出的八路緩沖器/驅(qū)動(dòng)器
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 147K
代理商: SN74AUCH240
SN74AUCH240
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES431A – MARCH 2003 – REVISED MARCH 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
I
off
Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max t
pd
of 1.7 ns at 1.8 V
Low Power Consumption, 20-
μ
A Max I
CC
±
8-mA Output Drive at 1.8 V
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This octal buffer/driver is operational at 0.8-V to 2.7-V V
CC
, but is designed specifically for 1.65-V to 1.95-V V
CC
operation.
The SN74AUCH240 is designed specifically to improve the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
This device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low,
the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40
°
C to 85
°
C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
QFN – RGY
Tape and reel
SN74AUCH240RGYR
MT240
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
RGY PACKAGE
(TOP VIEW)
1
20
10
11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
1
2
V
G
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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