參數(shù)資料
型號(hào)： SN74AUCH16374DGGR
廠商： TEXAS INSTRUMENTS INC
元件分類： 總線收發(fā)器
英文描述： AUC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48
封裝： GREEN, PLASTIC, TSSOP-48
文件頁(yè)數(shù)： 12/15頁(yè)
文件大?。?/td> 466K
代理商： SN74AUCH16374DGGR
www.ti.com
Timing Requirements
Switching Characteristics
Operating Characteristics
(1)
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2005
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
VCC = 0.8 V
± 0.1 V
± 0.15 V
± 0.2 V
UNIT
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
85
250
MHz
tw
Pulse duration, CLK high or low
5.9
1.9
ns
tsu
Setup time, data before CLK
↑
1.4
1.2
0.7
0.6
ns
th
Hold time, data after CLK
↑
0.1
0.4
ns
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
VCC = 0.8 V
FROM
TO
± 0.1 V
± 0.15 V
± 0.2 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
fmax
85
250
MHz
tpd
CLK
Q
7.3
1
4.5
0.8
2.9
0.7
1.5
2.8
0.7
2.2
ns
ten
OE
Q
7
1.2
5.3
0.8
3.6
0.8
1.5
2.9
0.7
2.2
ns
tdis
OE
Q
8.2
2
7.1
1
4.8
1.4
2.7
4.5
0.5
2.2
ns
T
A = 25°C
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
TEST CON-
PARAMETER
UNIT
DITIONS
TYP
1 fdata = 5 MHz,
Outputs
Cpd(2)
Power
1 fclk = 10 MHz,
enabled,
(each
dissipation
1 fout = 5 MHz,
24
24.1
26.2
31.2
pF
1 output
output)
capacitance
OE = GND,
switching
CL = 0 pF
Outputs
1 fdata = 5 MHz,
disabled,
1 fclk = 10 MHz,
Power
Cpd
1 clock
fout = not
dissipation
7.5
8
9.4
13.2
pF
(Z)
and 1
switching,
capacitance
data
OE = VCC,
switching CL = 0 pF
1 fdata = 0 MHz,
Outputs
1 fclk = 10 MHz,
Cpd(3)
Power
disabled,
fout = not
(each
dissipation
clock
13.8
14
14.7
17.5
pF
switching,
clock)
capacitance
only
OE = VCC,
switching
CL = 0 pF
(1)
Total device Cpd for multiple (n) outputs switching and (y) clocks inputs switching = {n * Cpd (each output)} + {y * Cpd (each clock)}.
(2)
Cpd (each output) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (Note: the clock is operating at 10 MHz
in this test, but its ICC component has been subtracted out).
(3)
Cpd (each clock) is the Cpd for the clock circuitry only as it operates at 10 MHz.
6
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