參數(shù)資料
型號(hào)： SN74ALVTH16501DGG
廠商： Texas Instruments, Inc.
英文描述： 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
中文描述： 2.5-V/3.3-V 18位通用總線收發(fā)器與三態(tài)輸出
文件頁(yè)數(shù)： 1/11頁(yè)
文件大?。?/td> 164K
代理商： SN74ALVTH16501DGG
SN54ALVTH16501, SN74ALVTH16501
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES071D – JUNE 1996 – REVISED JANUARY 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus
Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V
CC
)
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
High Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V
CC
)
Power Off Disables Outputs, Permitting
Live Insertion
High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
CC
+ 0.5 V
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The ’ALVTH16501 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V V
CC
operation, but
with the capability to provide a TTL interface to a 5-V system environment.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the
B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
P
Copyright
1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UBT and Widebus are trademarks of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
GND
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
GND
SN54ALVTH16501 . . . WD PACKAGE
SN74ALVTH16501 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
相關(guān)PDF資料
PDF描述
SN74ALVTH16501DGV 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ALVTH16501DL 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74AS00A Quadruple 2-Input Positive-Nand Gates(四2輸入正與非門)
SN74AS1008ADR QUADRUPLE 2-INPUT POSITIVE-AND BUFFER/DRIVER
SN74AS1008ADRE4 QUADRUPLE 2-INPUT POSTITIVE-AND BUFFER/DRIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74ALVTH16601DL 功能描述:通用總線函數(shù) 2.5/3.3V 18-Bit Univ Bus Trncvr W/3St Otp RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVTH16601DLR 功能描述:通用總線函數(shù) 2.5/3.3V 18bit Univ RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVTH16601GR 功能描述:通用總線函數(shù) 2.5/3.3V 18bit Univ RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVTH16601VR 功能描述:通用總線函數(shù) 2.5/3.3V 18bit Univ RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVTH16821DL 功能描述:觸發(fā)器 2.5/3.3V 20bit Univ RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*