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參數(shù)資料
| 型號(hào)： | SN74ALVCHR16409LR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 9-BIT EXCHANGER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.300 INCH, GREEN, PLASTIC, SSOP-56 |
| 文件頁(yè)數(shù)： | 1/17頁(yè) |
| 文件大小： | 354K |
| 代理商： | SN74ALVCHR16409LR |
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DGG OR DL PACKAGE
(TOP VIEW)
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PRE
SEL0
1A1
GND
1A2
1A3
VCC
1A4
1A5
1A6
GND
1A7
1A8
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2A9
SEL1
SEL2
CLK
SELEN
1B1
GND
1B2
1B3
VCC
1B4
1B5
1B6
GND
1B7
1B8
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2B9
SEL4
SEL3
The data-flow control logic is designed to allow glitch-free data transmission.
SN74ALVCHR16409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES056H – SEPTEMBER 1995 – REVISED OCTOBER 2004
Member of the Texas Instruments Widebus+
Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
B-Port Outputs Have Equivalent 26-
Series
Resistors, So No External Resistors Are
Required
UBE (Universal Bus Exchanger) Allows
Synchronous Data Exchange
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR, and the DLR package is
abbreviated to LR.
This 9-bit, 4-port universal bus exchanger is designed
for 1.65-V to 3.6-V VCC operation.
The SN74ALVCHR16409 allows synchronous data
exchange between four different buses. Data flow is
controlled by the select (SEL0-SEL4) inputs. A
data-flow state is stored on the rising edge of the
clock (CLK) input if the select-enable (SELEN) input
is low. Once a data-flow state has been established,
data is stored in the flip-flop on the rising edge of
CLK if SELEN is high.
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-
series resistors to reduce
overshoot and undershoot.
When preset (PRE) transitions high, the outputs are disabled immediately, without waiting for a clock pulse. To
leave the high-impedance state, both PRE and SELEN must be low, and a clock pulse must be applied.
To ensure the high-impedance state during power up or power down, PRE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCHR16409 is characterized for operation from -40
°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, EPIC, UBE are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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