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參數(shù)資料
| 型號： | SN74ALVCH374DBRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | GREEN, PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 484K |
| 代理商： | SN74ALVCH374DBRG4 |
www.ti.com
FEATURES
DB, DGV, DW, N, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
DESCRIPTION/ORDERING INFORMATION
SN74ALVCH374
OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES118G – JULY 1997 – REVISED OCTOBER 2004
Operates From 1.65 V to 3.6 V
Max tpd of 3.6 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels
at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
PDIP - N
Tube
SN74ALVCH374N
Tube
SN74ALVCH374DW
SOIC - DW
ALVCH374
Tape and reel
SN74ALVCH374DWR
-40
°C to 85°C
SSOP - DB
Tape and reel
SN74ALVCH374DBR
VB374
Tube
SN74ALVCH374PW
TSSOP - PW
VB374
Tape and reel
SN74ALVCH374PWR
TVSOP - DGV
Tape and reel
SN74ALVCH374DGVR
VB374
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 1997–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74ALVCH374DWR | ALVC/VCX/A SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| SN74ALVCH374N | ALVC/VCX/A SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20 |
| SN74ALVCH374PWRG4 | ALVC/VCX/A SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| SN74ALVCH374DBRE4 | ALVC/VCX/A SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| SN74ALVCHG162282GR | ALVC/VCX/A SERIES, 18-BIT EXCHANGER, TRUE OUTPUT, PDSO80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ALVCH374DGVR | 功能描述:觸發(fā)器 Octal Pos-Edge-Trig D-Type F-F RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| SN74ALVCH374DW | 功能描述:觸發(fā)器 Octal Pos-Edge-Trig D-Type F-F RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| SN74ALVCH374DWE4 | 功能描述:觸發(fā)器 Octal Pos-Edge-Trig D-Type F-F RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| SN74ALVCH374DWG4 | 功能描述:觸發(fā)器 Octal POS Edge TRIGRD DTyp FlipFlop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| SN74ALVCH374DWR | 功能描述:觸發(fā)器 Octal Pos-Edge-Trig D-Type F-F RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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