參數(shù)資料
型號(hào): SN74ALVCH16541DGGR
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48
封裝: PLASTIC, TSSOP-48
文件頁(yè)數(shù): 1/7頁(yè)
文件大?。?/td> 460K
代理商: SN74ALVCH16541DGGR
SN74ALVCH16541
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES031B – JULY 1995 – REVISED FEBRUARY 1999
3–205
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus
Family
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit buffer/driver is designed for 1.65-V to
3.6-V VCC operation.
The SN74ALVCH16541 is a noninverting 16-bit
buffer composed of two 8-bit sections with
separate output-enable signals. For either 8-bit
buffer section, the output enables (1OE1 and
1OE2 or 2OE1 and 2OE2) must both be low for the
corresponding Y outputs to be active. If either
output-enable input is high, the outputs of that
8-bit buffer section are in the high-impedance
state.
To ensure the high-impedance state during power
up or power down, OE should be tied to VCC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold
unused or floating data inputs at a valid logic level.
The SN74ALVCH16541 is characterized for
operation from –40
°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OUTPUT
OE1
OE2
A
Y
L
LH
H
XX
Z
X
H
X
Z
PRODUCT
PREVIEW
Copyright
1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
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48
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1OE1
1Y1
1Y2
GND
1Y3
1Y4
VCC
1Y5
1Y6
GND
1Y7
1Y8
2Y1
2Y2
GND
2Y3
2Y4
VCC
2Y5
2Y6
GND
2Y7
2Y8
2OE1
1OE2
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE2
DGG OR DL PACKAGE
(TOP VIEW)
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