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參數(shù)資料
| 型號： | SN74ALVC74PW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET |
| 中文描述： | 雙上升沿觸發(fā)的D型倒裝有明確和預(yù)設(shè)次浮點運算 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 127K |
| 代理商： | SN74ALVC74PW |
SN74ALVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES109E – JULY 1997 – REVISED JANUARY 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
description
This dual positive-edge-triggered D-type flip-flop
is designed for 1.65-V to 3.6-V V
CC
operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input may be changed without affecting the levels at the outputs.
The SN74ALVC74 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
H
L
L
X
↑
↑
L
X
H
H
H
H
H
L
H
H
L
L
H
H
H
X
Q0
Q0
This configuration is unstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic symbol
S
4
3
1CLK
1D
2
1D
R
1
1Q
5
6
C1
10
11
2CLK
12
2D
13
2Q
9
8
1PRE
2PRE
1CLR
2CLR
1Q
2Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
P
Copyright
1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
EPIC is a trademark of Texas Instruments Incorporated.
D, DGV, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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| SN74ALVC7803-20DL | 功能描述:先進先出 3.3V ABT 16-Bit Buff/Drv W/3-St Otpt RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7803-20DLR | 功能描述:先進先出 512 x 18 3.3-V Synch 先進先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7803-25DL | 功能描述:先進先出 16-Bit Buffer/Driver With 3-State Outputs RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7803-25DLR | 功能描述:先進先出 512 x 18 3.3-V Synch 先進先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7803-40DL | 功能描述:先進先出 16-Bit Bus Trnscvr With 3-State Outputs RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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