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參數(shù)資料
| 型號(hào)： | SN74ALVC16823 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 18 Bit Bus-Interface Triggers With 3-State Outputs(18位總線接口觸發(fā)器（三態(tài)輸出）) |
| 中文描述： | 18位總線接口，具有3觸發(fā)器態(tài)輸出（18位總線接口觸發(fā)器（三態(tài)輸出）） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 126K |
| 代理商： | SN74ALVC16823 |
SN74ALVC16823
18-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS270 – JANUARY 1993 – REVISED MARCH 1994
Copyright
1994, Texas Instruments Incorporated
9–1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Designed to Facilitate Incident-Wave
Switching for Line Impedances of 50
or Greater
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Bus-Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 18-bit bus-interface flip-flop is designed for
2.7-V to 3.6-V V
CC
operation.
The SN74ALVC16823 features 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing wider buffer registers,
I/O ports, bidirectional bus drivers with parity, and
working registers.
The SN74ALVC16823 can be used as two 9-bit
flip-flops or one 18-bit flip-flop. With the
clock-enable (CLKEN) input low, the D-type
flip-flops enter data on the low-to-high transitions
of the clock. Taking CLKEN high disables the clock
buffer, thus latching the outputs. Taking the clear
(CLR) input low causes the Q outputs to go low
independently of the clock.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
need for interface or pullup components.
The output-enable (OE) input does not affect the internal operation of the flip-flops. Old data can be retained
or new data can be entered while the outputs are in the high-impedance state.
The SN74ALVC16823 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same
printed-circuit-board area.
The SN74ALVC16823 is characterized for operation from –40
°
C to 85
°
C.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
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7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
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48
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38
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36
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34
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32
31
30
29
1CLR
1OE
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2OE
2CLR
1CLK
1CLKEN
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2CLKEN
2CLK
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
P
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|---|---|
| SN74ALVC16834DGGR | 功能描述:通用總線函數(shù) 16bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVC16834DGVR | 功能描述:通用總線函數(shù) 18bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVC16834DL | 功能描述:通用總線函數(shù) 18bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVC16834DLG4 | 功能描述:通用總線函數(shù) 18bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVC16834DLR | 功能描述:總線收發(fā)器 18-Bit Univ Bus Drv With 3-State Outputs RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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