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參數(shù)資料
| 型號(hào)： | SN74ALVC16600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 18-Bit Universal Bus Transceivers With 3-State Outputs(18位通用總線收發(fā)器（三態(tài)輸出）) |
| 中文描述： | 18位通用總線收發(fā)器與三態(tài)輸出（18位通用總線收發(fā)器（三態(tài)輸出）） |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 95K |
| 代理商： | SN74ALVC16600 |
SN74ALVC16600
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS263A – JANUARY 1993 – REVISED MARCH 1994
Copyright
1994, Texas Instruments Incorporated
9–1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Designed to Facilitate Incident-Wave
Switching for Line Impedances of 50
or Greater
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Bus-Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 18-bit universal bus transceiver is designed
for 2.7-V to 3.6-V V
CC
operation.
The SN74ALVC16600 combines D-type latches
and D-type flip-flops to allow data flow in
transparent, latched, and clocked modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B
data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is
latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop
on the high-to-low transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are
active. When OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA.
The SN74ALVC16600 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same
printed-circuit-board area.
The SN74ALVC16600 is characterized for operation from –40
°
C to 85
°
C.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
CLKENAB
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
CLKENBA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.
P
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| SN74ALVC16834DGGR | 功能描述:通用總線函數(shù) 16bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVC16834DGVR | 功能描述:通用總線函數(shù) 18bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVC16834DL | 功能描述:通用總線函數(shù) 18bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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