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參數(shù)資料
| 型號(hào)： | SN74AHCT373DGV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 中文描述： | 有三態(tài)輸出的8個(gè)透明D型鎖存器 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 534K |
| 代理商： | SN74AHCT373DGV |
SN54AHCT373, SN74AHCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS239M – OCTOBER 1995 – REVISED JULY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Inputs Are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN54AHCT373 . . . J OR W PACKAGE
SN74AHCT373 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54AHCT373 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
2Q
3Q
3D
4D
1
1
O
5
5
8
4
G
L
V
C
8D
7D
7Q
6Q
6D
description/ordering information
The ’AHCT373 devices are octal-transparent D-type latches. When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74AHCT373N
SN74AHCT373N
SOIC – DW
Tube
SN74AHCT373DW
AHCT373
Tape and reel
SN74AHCT373DWR
–40
°
C to 85
°
C
SOP – NS
Tape and reel
SN74AHCT373NSR
AHCT373
SSOP – DB
Tape and reel
SN74AHCT373DBR
HB373
TSSOP – PW
Tube
SN74AHCT373PW
HB373
Tape and reel
SN74AHCT373PWR
TVSOP – DGV
Tape and reel
SN74AHCT373DGVR
HB373
CDIP – J
Tube
SNJ54AHCT373J
SNJ54AHCT373J
–55
°
C to 125
°
C
CFP – W
Tube
SNJ54AHCT373W
SNJ54AHCT373W
LCCC – FK
Tube
SNJ54AHCT373FK
SNJ54AHCT373FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74AHCT373DGVR | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 12pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: 100% Tin (Sn); Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: M Failure Rate |
| SN54AHCT86FK | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
| SN54AHCT86J | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
| SN54AHCT86W | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
| SN74AHCT86DB | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74AHCT373DW | 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74AHCT373DWE4 | 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74AHCT373DWG4 | 功能描述:閉鎖 Octal Transp DType Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74AHCT373DWR | 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74AHCT373DWRE4 | 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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