參數資料
型號: SN74AHC32QPWRQ1
廠商: Texas Instruments
文件頁數: 10/14頁
文件大?。?/td> 0K
描述: IC QUAD 2-IN POS-OR GATE 14TSSOP
標準包裝: 1
系列: 74AHC
邏輯類型: 或門
電路數: 4
輸入數: 2
電源電壓: 2 V ~ 5.5 V
電流 - 靜態(tài)(最大值): 2µA
輸出電流高,低: 8mA,8mA
邏輯電平 - 低: 0.5 V ~ 1.65 V
邏輯電平 - 高: 1.5 V ~ 3.85 V
額定電壓和最大 CL 時的最大傳播延遲: 7.5ns @ 5V,50pF
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
供應商設備封裝: 14-TSSOP
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 標準包裝
其它名稱: 296-17540-6
SN74AHC32QQ1
QUADRUPLE 2INPUT POSITIVEOR GATE
SGDS019A FEBRUARY 2002 REVISED APRIL 2008
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPLH
VOH
VOL
VCC
0 V
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC
VOL + 0.3 V
50% VCC
≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST
S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 1 MHz, ZO = 50 , tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL = 1 k
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
VOH 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
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