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參數(shù)資料
| 型號： | SN74ACT53861 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4096×18 Clocked Multiple-Queue (MULTI-QE) FIRST-IN, FIRST-OUT Memory(4096×18定時多重隊列FIFO存儲器() |
| 中文描述： | 4096 × 18時鐘多隊列（多量子效率）先入先出存儲器（4096 × 18定時多重隊列先進先出存儲器（） |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 558K |
| 代理商： | SN74ACT53861 |
SN74ACT53861
4096
×
18 CLOCKED MULTIPLE-QUEUE (MULTI-Q
) FIRST-IN, FIRST-OUT MEMORY
WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FLAGS
SCAS443A – JUNE 1994 – REVISED JULY 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4096
×
18 Total Memory Size
Three Programmable-Depth FIFOs on One
Device
Memory Allocation of 256
×
18 Blocks
Two Separate Read and Write Clocks
That Can Operate Synchronously or
Asynchronously
Clocked Interface; Read and Write Enables
Synchronize Data Transfers to Continuous
Clocks
Programmable Cell Size From 10 to 32
18-Bit Words
Cell-Abort Feature to Discard a Previous
Cell Write
Cell-Ready Flag for Each Queue
Synchronized to Read Clock
Programmable Flag With Hysteresis for
Each Queue Synchronized to Write Clock
Last Word of Cell Flag Synchronized to
Read Clock
Input or Output Bus Size of 9 Bits or
18 Bits, Byte Stuff/Destuff Capability
Data Access Times of 11 ns
Synchronous Multiplexer for Queue Output
Selection
8-bit Bidirectional Programming Port
Clock Frequencies up to 50 MHz
Produced in 0.8-
μ
m Advanced CMOS
Technology
Available in 100-Pin Thin Quad Flat (PZ)
Package
description
The Multi-Q FIFO is a first-in, first-out (FIFO) memory with three programmable-length queues and a total
memory size of 4096 words of 18 bits each to provide two or three quality of service (QOS) bins for ATM traffic
in a single device. The core memory is divided into sixteen 256 x 18 blocks that can be allocated to each queue
according to the user’s need.
Flags for the queues are designed to indicate the presence or absence of entire cells rather than individual
words. The number of 18-bit words that constitutes one cell is programmable by the user and has a default value
of 27. A cell-ready (CR) flag for a queue is high when at least one complete cell is present in the queue. Each
CR flag is synchronized to the read clock (RDCLK). The full flag (FF) for each queue is synchronized to the write
clock (WRTCLK) and indicates when no more cells can be written to the queue. A programmable flag (PF) is
provided for each queue, which is synchronized to the WRTCLK. Each PF has two programmable values. PF
is low when the number of cells in the queue are greater than or equal to the first limit, and it is set high when
the number of cells in the queue are reduced to the second limit. This allows the user to define a hysteresis
threshold for the flag if it is needed.
WRTCLK and RDCLK are designed to be free-running clock inputs to maintain the proper synchronization of
the flags. The clocks are synchronized or asynchronous in phase, frequency, or both. Writes to one of the three
queues is done by a rising edge of WRTCLK when the queue’s write enable (WRTEN) is high. Any write can
be done to two or three of the queues simply by asserting two or three of the WRTEN inputs for a WRTCLK rising
edge. Data is read from a queue by the rising edge of RDCLK when the queue is selected by the multiplexer
(MUX0, MUX1) inputs and the read enable (RDEN) is high. Configuration registers can be programmed to set
the input or output port sizes to 9 bits or 18 bits. Big- or little-endian data format can be selected for the buses.
When matching 9-bit buses to 18-bit or 36-bit buses with the Multi-Q, byte stuffing can be selected for the data
input and byte destuffing can be done on the data output.
Copyright
1995, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Multi-Q is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
P
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