參數(shù)資料
型號: SN74ABT8952DLRG4
廠商: Texas Instruments
文件頁數(shù): 3/31頁
文件大?。?/td> 0K
描述: IC SCAN TESST DEVICE 28-SSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: 74ABT
邏輯類型: 掃描測試設(shè)備,帶寄存總線收發(fā)器
電源電壓: 4.5 V ~ 5.5 V
位數(shù): 8
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 帶卷 (TR)
SN54ABT8952, SN74ABT8952
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS121D – AUGUST 1992 – REVISED JULY 1996
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
instruction-register opcode description
The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of
each instruction.
Table 3. Instruction-Register Opcodes
BINARY CODE
BIT 7
→ BIT 0
MSB
→ LSB
SCOPE OPCODE
DESCRIPTION
SELECTED DATA
REGISTER
MODE
00000000
EXTEST/INTEST
Boundary scan
Test
10000001
BYPASS
Bypass scan
Bypass
Normal
10000010
SAMPLE/PRELOAD
Sample boundary
Boundary scan
Normal
00000011
INTEST/EXTEST
Boundary scan
Test
10000100
BYPASS
Bypass scan
Bypass
Normal
00000101
BYPASS
Bypass scan
Bypass
Normal
00000110
HIGHZ
Control boundary to high impedance
Bypass
Modified test
10000111
CLAMP
Control boundary to 1/0
Bypass
Test
10001000
BYPASS
Bypass scan
Bypass
Normal
00001001
RUNT
Boundary run test
Bypass
Test
00001010
READBN
Boundary read
Boundary scan
Normal
10001011
READBT
Boundary read
Boundary scan
Test
00001100
CELLTST
Boundary self test
Boundary scan
Normal
10001101
TOPHIP
Boundary toggle outputs
Bypass
Test
10001110
SCANCN
Boundary-control register scan
Boundary control
Normal
00001111
SCANCT
Boundary-control register scan
Boundary control
Test
All others
BYPASS
Bypass scan
Bypass
Normal
Bit 7 is used to maintain even parity in the 8-bit instruction.
The BYPASS instruction is executed in lieu of a SCOPE
instruction that is not supported in the ’ABT8952.
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned
into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into
the output BSCs is applied to the device output pins. The device operates in the test mode.
bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the
normal mode.
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