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參數(shù)資料
| 型號： | SN74ABT7819PN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
| 中文描述： | 512】18】2時鐘雙向先入先出存儲器 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 284K |
| 代理商： | SN74ABT7819PN |
SN74ABT7819
512
×
18
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125G – JULY 1992 – REVISED JULY 1998
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
enable logic diagram (positive logic)
CSA
W/RA
WENA
RENA
WEN FIFOA–B
A0–A17 (output enable)
REN FIFOB–A
CSB
W/RB
WENB
RENB
WEN FIFOB–A
B0–B17 (output enable)
REN FIFOA–B
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
A0–A17
7–8, 10–11,
13–14, 16–17,
19–20, 22–23,
25–26, 28–29,
31–32
I/O
Port-A data. The 18-bit bidirectional data port for side A.
AF/AEA
3
O
FIFOA–B almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEA or the default
value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEA is
high when X or fewer words or (512 – Y) or more words are stored in FIFOA–B. AF/AEA is forced high
when FIFOA–B is reset.
AF/AEB
62
O
FIFOB–A almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEB or the default
value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEB is
high when X or fewer words or (512 – Y) or more words are stored in FIFOB–A. AF/AEB is forced high
when FIFOB–A is reset.
B0–B17
58–57, 55–54,
52–51, 49–48,
46–45, 43–42,
40–39, 37–36,
34–33
I/O
Port-B data. The 18-bit bidirectional data port for side B.
CLKA
76
I
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A to its
low-to-high transition and can be asynchronous or coincident to CLKB.
CLKB
69
I
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B to its
low-to-high transition and can be asynchronous or coincident to CLKA.
CSA
80
I
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to either write data from
A0–A17 to FIFOA–B or read data from FIFOB–A to A0–A17. The A0–A17 outputs are in the
high-impedance state when CSA is high.
CSB
65
I
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to either write data from
B0–B17 to FIFOB–A or read data from FIFOA–B to B0–B17. The B0–B17 outputs are in the
high-impedance state when CSB is high.
Terminals listed are for the PH package.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ABT7820-15N | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| SN74ABT7820-15PH | 功能描述:先進先出 512 x 18 x 2 bidir ASynch 先進先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ABT7820-15PN | 功能描述:先進先出 512 x 18 x 2 bidir ASynch 先進先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ABT7820-20PH | 功能描述:先進先出 512 x 18 x 2 bidir ASynch 先進先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ABT7820-20PN | 功能描述:先進先出 512 x 18 x 2 bidir ASynch 先進先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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