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參數(shù)資料
| 型號： | SN74ABT7819PH |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
| 中文描述： | 512】18】2時鐘雙向先入先出存儲器 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 284K |
| 代理商： | SN74ABT7819PH |
SN74ABT7819
512
×
18
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125G – JULY 1992 – REVISED JULY 1998
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
HFA
4
O
FIFOA–B half-full flag. HFA is high when FIFOA–B contains 256 or more words and is low when
FIFOA–B contains 255 or fewer words. HFA is set low after FIFOA–B is reset.
HFB
61
O
FIFOB–A half-full flag. HFB is high when FIFOB–A contains 256 or more words and is low when
FIFOB–A contains 255 or fewer words. HFB is set low after FIFOB–A is reset.
IRA
5
O
Port-A input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low,
FIFOA–B is full and writes to its array are disabled. IRA is set low during a FIFOA–B reset and is set high
on the second low-to-high transition of CLKA after reset.
IRB
60
O
Port-B input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low,
FIFOB–A is full and writes to its array are disabled. IRB is set low during a FIFOB–A reset and is set high
on the second low-to-high transition of CLKB after reset.
ORA
74
O
Port-A output-ready flag. ORA is synchronized to the low-to-high transition of CLKA. When ORA is low,
FIFOB–A is empty and reads from its array are disabled. The last valid word remains on the FIFOB–A
outputs when ORA is low. Ready data is present for the A0–A17 outputs when ORA is high. ORA is set
low during a FIFOB–A reset and goes high on the third low-to-high transition of CLKA after the first word
is loaded to an empty FIFOB–A.
ORB
71
O
Port-B output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low,
FIFOA–B is empty and reads from its array are disabled. The last valid word remains on the FIFOA–B
outputs when ORB is low. Ready data is present for the B0–B17 outputs when ORB is high. ORB is set
low during a FIFOA–B reset and goes high on the third low-to-high transition of CLKB after the first word
is loaded to an empty FIFOA–B.
PENA
2
I
AF/AEA program enable. After FIFOA–B is reset and before a word is written to its array, the binary value
on A0–A7 is latched as an AF/AEA offset when PENA is low and CLKA is high.
PENB
63
I
AF/AEB program enable. After FIFOB–A is reset and before a word is written to its array, the binary value
on B0–B7 is latched as an AF/AEB offset when PENB is low and CLKB is high.
RENA
75
I
Port-A read enable. A high level on RENA enables data to be read from FIFOB–A on the low-to-high
transition of CLKA when CSA is low, W/RA is low, and ORA is high.
RENB
70
I
Port-B read enable. A high level on RENB enables data to be read from FIFOA–B on the low-to-high
transition of CLKB when CSB is low, W/RB is low, and ORB is high.
RSTA
1
I
FIFOA–B reset. To reset FIFOA–B, four low-to-high transitions of CLKA and four low-to-high transitions
of CLKB must occur while RSTA is low. This sets HFA low, IRA low, ORB low, and AF/AEA high.
RSTB
64
I
FIFOB–A reset. To reset FIFOB–A, four low-to-high transitions of CLKA and four low-to-high transitions
of CLKB must occur while RSTB is low. This sets HFB low, IRB low, ORA low, and AF/AEB high.
WENA
77
I
Port-A write enable. A high level on WENA enables data on A0–A17 to be written into FIFOA–B on the
low-to-high transition of CLKA when W/RA is high, CSA is low, and IRA is high.
WENB
68
I
Port-B write enable. A high level on WENB enables data on B0–B17 to be written into FIFOB–A on the
low-to-high transition of CLKB when W/RB is high, CSB is low, and IRB is high.
W/RA
79
I
Port-A write/read select. A high on W/RA enables A0–A17 data to be written to FIFOA–B on a low-to-high
transition of CLKA when WENA is high, CSA is low, and IRA is high. A low on W/RA enables data to be
read from FIFOB–A on a low-to-high transition of CLKA when RENA is high, CSA is low, and ORA is high.
The A0–A17 outputs are in the high-impedance state when W/RA is high.
W/RB
66
I
Port-B write/read select. A high on W/RB enables B0–B17 data to be written to FIFOB–A on a low-to-high
transition of CLKB when WENB is high, CSB is low, and IRB is high. A low on W/RB enables data to be
read from FIFOA–B on a low-to-high transition of CLKB when RENB is high, CSB is low, and ORB is high.
The B0–B17 outputs are in the high-impedance state when W/RB is high.
Terminals listed are for the PH package.
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參數(shù)描述 |
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| SN74ABT7820-15N | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| SN74ABT7820-15PH | 功能描述:先進(jìn)先出 512 x 18 x 2 bidir ASynch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ABT7820-15PN | 功能描述:先進(jìn)先出 512 x 18 x 2 bidir ASynch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ABT7820-20PH | 功能描述:先進(jìn)先出 512 x 18 x 2 bidir ASynch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ABT7820-20PN | 功能描述:先進(jìn)先出 512 x 18 x 2 bidir ASynch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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