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參數(shù)資料
| 型號(hào)： | SN74ABT574AZQNR |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:47; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:40; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:40-9 RoHS Compliant: No |
| 中文描述： | 八路邊沿觸發(fā)的D型倒裝3觸發(fā)器態(tài)輸出 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 764K |
| 代理商： | SN74ABT574AZQNR |
SCBS191F JANUARY 1991 REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The eight flip-flops of the SN54ABT574 and SN74ABT574A are edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
terminal assignments
1
2
3
4
A
1D
OE
VCC
2D
1Q
B
3D
3Q
2Q
C
5D
4D
5Q
4Q
D
7D
7Q
6D
6Q
E
GND
8D
CLK
8Q
FUNCTION TABLE
(each flip-flop)
INPUTS
CLK
↑
↑
H or L
OUTPUT
Q
OE
D
L
H
H
L
L
L
L
X
Q0
Z
H
X
X
logic diagram (positive logic)
OE
CLK
1D
1Q
To Seven Other Channels
C1
1
11
2
19
1D
Pin numbers shown are for the DB, DW, FK, J, N, NS, PW, RGY, and W packages.
SN74ABT574A . . . GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
4
A
B
C
D
E
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74ABT652DB | OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
| SN54ABT652FK | OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
| SN54ABT652JT | OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
| SN74ABT7819PH | 512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
| SN74ABT7819PN | 512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ABT574DW | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| SN74ABT574DWR | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| SN74ABT574N | 制造商:Texas Instruments 功能描述: |
| SN74ABT620DBR | 功能描述:總線收發(fā)器 Tri-State Octal Bus RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ABT620DBRE4 | 功能描述:總線收發(fā)器 Octal Bus Trnscvrs With 3-State Outputs RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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