參數(shù)資料
型號(hào)： SN65LVDS9637BDG4
廠(chǎng)商： TEXAS INSTRUMENTS INC
元件分類(lèi)： Buffer和線(xiàn)驅(qū)動(dòng)
英文描述： DUAL LINE RECEIVER, PDSO8
封裝： 1.27 MM PITCH, GREEN, SOIC-8
文件頁(yè)數(shù)： 6/22頁(yè)
文件大小： 358K
代理商： SN65LVDS9637BDG4
www.ti.com
APPLICATION INFORMATION
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
100
100
100
(see Note B)
100
VCC
See Note C
≈3.6 V
0.1
F
(see Note A)
1N645
(2 places)
0.01
F
5 V
RELATED INFORMATION
TERMINATED FAILSAFE
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
A.
Place a 0.1-F Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B.
The termination resistance value should match the nominal characteristic impedance of the transmission media with
±10%.
C.
Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 12. Operation with 5-V Supply
IBIS modeling is available for this device. contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For more application guidelines, see the following documents:
Low-Voltage Differential Signaling Design Notes (SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With RS-422 Data (SLLA031)
Evaluating the LVDS EVM (SLLA033)
A differential line receiver commonly has a fail-safe circuit to prevent it from switching on input noise. Current
LVDS fail-safe solutions require either external components with subsequent reduction in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated fail-safe that solves
the limitations seen in present solutions. A detailed theory of operation is presented in application note The
Active Fail-Safe Feature of the SN65LVDS32A (SLLA082).
Figure 13 shows one receiver channel with active fail-safe. It consists of a main receiver that can respond to a
high-speed input differential signal. Also connected to the input pair are two fail-safe receivers that form a
window comparator. The window comparator has a much slower response than the main receiver and detects
when the input differential falls below 80 mV. A 600-ns fail-safe timer filters the window comparator outputs.
When fail-safe is asserted, the fail-safe logic drives the main receiver output to logic high.
14
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