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參數(shù)資料
| 型號： | SN65LVDS94DGGG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LVDS SERDES RECEIVER 56-TSSOP |
| 標準包裝： | 35 |
| 系列： | 65LVDS |
| 功能： | 串行器/解串器 |
| 輸入類型： | LVDS |
| 輸出類型： | LVTTL |
| 輸入數(shù)： | 4 |
| 輸出數(shù)： | 28 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 56-TSSOP |
| 包裝： | 管件 |
www.ti.com
SN74FB2032
8
D0–D7
8
D8–D15
SN75LVDS93
LVDS
Interface
0 To 10 Meters
(Media Dependent)
TTL
Interface
W/Parity
16-Bit
BTL Bus
Interface
CLK
Backplane
Bus
8
D0–D7
8
D8–D15
CLK
Backplane
Bus
TTL
Interface
16-Bit
BTL Bus
Interface
XMIT Clock
RCV Clock
9 Bit Latchable
Transceiver/ With
Parity Generator
Parity
TTL
Interface
Parity
Error
TTL
Interface
W/Parity
SN74FB2032
9 Bit Latchable
Transceiver/ With
Parity Generator
SN74FB2032
9 Bit Latchable
Transceiver/ With
Parity Generator
9 Bit Latchable
Transceiver/ With
Parity Generator
SN75LVDS94
LOW COST VIRTUAL BACKPLANE TRANSCEIVER
Bus
Transceivers
LVDS Serdes
Transmitter
LVDS Serdes
Receiver
Bus
Transceivers
TTL
Inputs
Up To
21 or 28
Bits
LVDS
Serial Links
4 or 5
Pairs
TTL
Outputs
Up To
21 or 28
Bits
Bus
Transceivers
LVDS Serdes
Transmitter
LVDS Serdes
Receiver
Bus
Transceivers
Backplane
Bus
Backplane
Bus
SLLS298F – MAY 1998 – REVISED JANUARY 2006
APPLICATION INFORMATION (continued)
Figure 12. 16-Bit Bus Extension With Parity
Figure 13 represents LVDS serdes in an application as a virtual backplane transceiver (VBT). The concept of a
VBT can be achieved by implementing individual LVDS serdes chipsets in both directions of subsystem
serialized links.
Depending on the application, the designer will face varying choices when implementing a VBT. In addition to the
devices shown in Figure 13, functions such as parity and delay lines for control signals could be included. Using
additional circuitry, half-duplex or full-duplex operation can be achieved by configuring the clock and control lines
properly.
The designer may choose to implement an independent clock oscillator at each end of the link and then use a
PLL to synchronize LVDS serdes's parallel I/O to the backplane bus. Resynchronizing FIFOs may also be
required.
Figure 13. Virtual Backplane Transceiver
12
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN65LVDS94DGG-P | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN65LVDS94DGGR | 功能描述:LVDS 接口集成電路 Serdes Receiver RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SN65LVDS94DGGRG4 | 功能描述:LVDS 接口集成電路 Serdes Receiver RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SN65LVDS95DGG | 功能描述:緩沖器和線路驅(qū)動器 Serdes Transmitter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN65LVDS95DGG | 制造商:Texas Instruments 功能描述:Transceiver IC Transceiver Type:Eia/Tia- |
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