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參數(shù)資料
| 型號： | SN65LVDS94DGG |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LVDS SERDES RCVR 56-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 35 |
| 系列： | 65LVDS |
| 功能： | 串行器/解串器 |
| 輸入類型： | LVDS |
| 輸出類型： | LVTTL |
| 輸入數(shù)： | 4 |
| 輸出數(shù)： | 28 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 906 (CN2011-ZH PDF) |
| 其它名稱： | 296-1430 296-1430-5 |
www.ti.com
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D22
D23
D24
GND
D25
D26
D27
LVDSGND
A0M
A0P
A1M
A1P
LVDSVCC
LVDSGND
A2M
A2P
CLKINM
CLKINP
A3M
A3P
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKOUT
D0
GND
VCC
D21
D20
D19
GND
D18
D17
D16
VCC
D15
D14
D13
GND
D12
D11
D10
VCC
D9
D8
D7
GND
D6
D5
D4
D3
VCC
D2
D1
DGG PACKAGE
(TOP VIEW)
DESCRIPTION
SLLS298F – MAY 1998 – REVISED JANUARY 2006
LVDS SERDES RECEIVER
4:28 Data Channel Expansion at up to 1.904
Gigabits per Second Throughput
Suited for Point-to-Point Subsystem
Communication With Very Low EMI
4 Data Channels and Clock Low-Voltage
Differential Channels in and 28 Data and
Clock Out Low-Voltage TTL Channels Out
Operates From a Single 3.3-V Supply and
250 mW (Typ)
5-V Tolerant SHTDN Input
Rising Clock Edge Triggered Outputs
Bus Pins Tolerate 4-kV HBM ESD
Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
Consumes <1 mW When Disabled
Wide Phase-Lock Input Frequency Range
20 MHz to 68 MHz
No External Components Required for PLL
Meets or Exceeds the Requirements of ANSI
EIA/TIA-644 Standard
Industrial Temperature Qualified
TA = -40°C to 85°C
Replacement for the DS90CR286
The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift
registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single
integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the
SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended
LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the
LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the
expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 1998–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN65LVDS94DGG | 制造商:Texas Instruments 功能描述:FLATLINK (TM) RECEIVER T/R |
| SN65LVDS94DGGG4 | 功能描述:LVDS 接口集成電路 Serdes Receiver RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SN65LVDS94DGG-P | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN65LVDS94DGGR | 功能描述:LVDS 接口集成電路 Serdes Receiver RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SN65LVDS94DGGRG4 | 功能描述:LVDS 接口集成電路 Serdes Receiver RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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