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參數(shù)資料
| 型號： | SN65HVD56D |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Relay Socket; For Use With:RUM F2xxxx and RUM F3xxxx Relays; Features:Separate terminals, Box Lug Connector; Series:RUZ RoHS Compliant: Yes |
| 中文描述： | 高輸出全雙工RS - 485驅(qū)動器和接收 |
| 文件頁數(shù)： | 9/23頁 |
| 文件大小： | 1547K |
| 代理商： | SN65HVD56D |
www.ti.com
THERMAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
(1)
PARAMETER MEASUREMENT INFORMATION
60
±
1%
V
O
D
0or3V
_
+
7V<V
(
t
e
s
t
)
<12V
DE
V
C
C
Y
Z
D
375
±
1%
375
±
1%
I
Y
V
O
D
R
L
0or3V
V
Y
V
Z
I
Z
DE
V
C
C
I
I
V
I
Y
Z
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
SLLS666–SEPTEMBER 2005
PARAMETER
TEST CONDITIONS
Low-K board
(3)
, No airflow
MIN
TYP
230.8
162.6
135.1
92.1
44.4
61.1
43.5
58.6
MAX
UNIT
HVD50, HVD51, HVD52, HVD56, HVD57
HVD53, HVD54, HVD55, HVD58, HVD59
HVD50, HVD51, HVD52, HVD56, HVD57
HVD53, HVD54, HVD55, HVD58, HVD59
HVD50, HVD51, HVD52, HVD56, HVD57
HVD53, HVD54, HVD55, HVD58, HVD59
HVD50, HVD51, HVD52, HVD56, HVD57
HVD53, HVD54, HVD55, HVD58, HVD59
HVD50, HVD56 (25Mbps)
HVD51, HVD57 (10Mbps)
HVD52 (1Mbps)
Junction–to–ambient
thermal resistance
(2)
θ
JA
High-K board
(4)
, No airflow
Junction–to–ambient
thermal resistance
(2)
°
C/W
Junction–to–board
thermal resistance
θ
JB
High-K board
Junction–to–case
thermal resistance
θ
JC
No board
R
= 60
, C
= 50 pF,
Input to D a 50% duty cycle
square wave at indicated
signaling rate
R
= 60
, C
= 50 pF,
DE at V
RE at 0 V,
Input to D a 50% duty cycle
square wave at indicated
signaling rate
Low-K board, No airflow
420
404
383
Device power
dissipation
P
D
mW
HVD53, HVD58 (25Mbps)
HVD54, HVD59 (10Mbps)
HVD55 (1Mbps)
420
404
383
HVD50, HVD56
HVD51, HVD52, HVD57
HVD53, HVD54, HVD55, HVD58, HVD59
HVD50, HVD51, HVD52, HVD56, HVD57
HVD53, HVD54, HVD55, HVD58, HVD59
–40
–40
–40
–40
–40
55
84
85
85
85
Ambient air
temperature
T
A
°
C
High-K board, No airflow
T
JSD
Thermal shutdown junction temperature
165
(1)
(2)
See
Application Information
section for an explanation of these parameters.
The intent of
θ
specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
(3)
(4)
Figure 1. Driver V
OD
Test Circuit: Voltage and Current
Definitions
Figure 2. Driver V
OD
With Common-Mode Loading Test
Circuit
9
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