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參數(shù)資料
| 型號(hào)： | SN65175N |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUADRUPLE DIFFERENTIAL LINE RECEIVERS |
| 中文描述： | 翻兩番差分線接收機(jī) |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大小： | 152K |
| 代理商： | SN65175N |
SN65175, SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS145B – OCTOBER 1990 – REVISED MAY 1995
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage and operating free-air temperature
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIT+
VIT–
Vhys
VIK
VOH
Positive-going input threshold voltage
VO = 2.7 V,
VO = 0.5 V,
See Figure 4
IO = –0.4 mA
IO = 16 mA
0.2
V
Negative-going input threshold voltage
–0.2
V
Hysteresis voltage (VIT+ – VIT–)
Enable-input clamp voltage
50
mV
II = –18 mA
VID = 200 mV,
–1.5
V
High-level output voltage
IOH = –400
μ
A,
See Figure 1
2.7
V
VOL
Low level output voltage
Low-level output voltage
VID=
200 mV
See Figure 1
IOL = 8 mA
IOL = 16 mA
0.45
V
0.5
±
20
IOZ
High-impedance-state output current
VO = 0.4 V to 2.4 V
μ
A
II
Line input current
Other input at 0 V,
See Note 3
VI = 12 V
VI = –7 V
1
mA
–0.8
IIH
IIL
ri
IOS
ICC
All typical values are at VCC = 5 V, TA = 25
°
C.
The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold voltage
levels only.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 3: Refer to ANSI Standards EIA/TIA-422-B, RS-423-B, and RS-485 for exact conditions.
High-level enable-input current
VIH = 2.7 V
VIL = 0.4 V
20
μ
A
μ
A
k
mA
Low-level enable-input current
–100
Input resistance
Short-circuit output current§
12
–15
–85
Supply current
Outputs disabled
70
mA
switching characteristics, V
CC
= 5 V, C
L
= 15 pF, T
A
= 25
°
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation delay time, low- to high-level output
See Figure 2
22
35
ns
Propagation delay time, high- to low-level output
25
35
ns
Output enable time to high level
See Figure 3
13
30
ns
Output enable time to low level
19
30
ns
Output disable time from high level
See Figure 3
26
35
ns
Output disable time from low level
25
35
ns
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