
SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS261F – JULY 1997 – REVISED MARCH 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN65LVDSxxxx electrical characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS31,
’3487, ’ 9638
TYP
247
UNIT
MIN
MAX
454
340
mV
VOD
Change in differential output voltage magnitude
between logic states
RL = 100
,
See Figure 2
–50
50
mV
VOC(SS)
Steady-state common-mode output voltage
See Figure 3
1.125
1.2
1.375
mV
VOC(SS)
Change in steady-state common-mode output voltage
between logic states
See Figure 3
–50
50
V
VOC(PP)
Peak-to-peak common-mode output voltage
50
150
mV
SN65LVDS31,
’3487
VI = 0.8 V or 2 V,
No load
Enabled,
9
20
mA
ICC
Supply current
VI = 0.8 or 2 V,
Enabled
RL = 100
,
25
35
mA
VI = 0 or VCC,
Disabled
0.25
1
mA
SN65LVDS9638
VI= 0 8 V or 2 V
VI = 0.8 V or 2 V
No load
RL = 100
4.7
8
mA
9
13
mA
μ
A
μ
A
mA
IIH
IIL
High-level input current
VIH = 2
VIL = 0.8 V
VO(Y) or VO(Z) = 0
VOD = 0
VO = 0 or 2.4 V
VCC = 0,
4
20
Low-level input current
0.1
10
IOS
Short circuit output current
Short-circuit output current
–4
–24
±
12
±
1
±
1
mA
μ
A
μ
A
IOZ
IO(OFF)
CI
All typical values are at TA = 25
°
C and with VCC = 3.3 V.
High-impedance output current
Power-off output current
VO = 2.4 V
Input capacitance
3
pF
SN65LVDSxxxx switching characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS31,
’3487, ’ 9638
TYP
0.5
UNIT
MIN
MAX
tpLH
tpHL
tr
tf
tsk(p)
tsk(o)
tsk(pp)
tpZH
tpZL
tpHZ
tpLZ
All typical values are at TA = 25
°
C and with VCC = 3.3 V.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical specified loads.
§tsk(pp) is the magnitude of the different in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, same temperature, and have identical packages and test circuits.
Propagation delay time, low-to-high-level output
1.4
2
ns
Propagation delay time, high-to-low-level output
1
1.7
2.5
ns
Differential output signal rise time (20% to 80%)
RL = 100
, CL
See Figure 2
0.4
0.5
0.6
ns
Differential output signal fall time (80% to 20%)
,
0.4
0.5
0.6
ns
Pulse skew (|tPHL – tPLH|)
Channel-to-channel output skew
Part-to-part skew§
0.3
0.6
ns
0
0.3
ns
800
ps
Propagation delay time, high-impedance-to-high-level output
5.4
15
ns
Propagation delay time, high-impedance-to-low-level output
See Figure 4
2.5
15
ns
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
8.1
7.3
15
15
ns
ns