參數(shù)資料
型號(hào): SN54LVTH652FK
廠商: Texas Instruments, Inc.
英文描述: Dual D-Type Flip-Flop with Set and Reset; Package: SOEIAJ-14; No of Pins: 14; Container: Rail; Qty per Container: 50
中文描述: 的3.3V ABT生根粉八路總線收發(fā)器和3冊(cè)態(tài)輸出
文件頁(yè)數(shù): 8/10頁(yè)
文件大?。?/td> 151K
代理商: SN54LVTH652FK
SN54LVTH652, SN74LVTH652
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS706D – AUGUST 1997 – REVISED APRIL 1999
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
SN54LVTH652
VCC = 3.3 V
±
0.3 V
SN74LVTH652
VCC = 3.3 V
±
0.3 V
VCC = 2.7 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
tw
Clock frequency
150
150
150
150
MHz
Pulse duration, CLK high or low
3.3
3.3
3.3
3.3
ns
tsu
Setup time,
A or B before CLKAB
or CLKBA
Data high
1.3
1.6
1.2
1.5
ns
Data low
1.9
2.6
1.6
2.2
th
Hold time, A or B after CLKAB
or CLKBA
1.2
1.2
0.8
0.8
ns
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 2)
SN54LVTH652
VCC = 3.3 V
±
0.3 V
SN74LVTH652
VCC = 3.3 V
±
0.3 V
TYP
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.7 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
150
150
150
150
MHz
CLKBA or
CLKAB
A or B
1.7
5
5.9
1.8
3.1
4.7
5.6
ns
1.7
5
5.9
1.8
3.1
4.7
5.6
A or B
B or A
1.2
3.7
4.3
1.3
2.3
3.5
4.1
ns
1.2
3.7
4.3
1.3
2.4
3.5
4.1
SBA or SAB
A or B
1.4
5.2
6.3
1.5
3.1
4.9
6
ns
1.4
5.2
6.3
1.5
3.4
4.9
6
OEBA
A
1
5.4
6.7
1.1
2.9
5.2
6.5
ns
1
5.4
6.7
1.1
3.1
5.2
6.5
OEBA
A
2.2
5.9
6.5
2.3
3.5
5.5
6.1
ns
2.2
5.9
6.3
2.3
3.7
5.5
5.9
OEAB
B
1.2
4.9
5.9
1.3
3
4.7
5.7
ns
1.2
4.9
5.9
1.3
3.3
4.7
5.7
OEAB
B
1.4
1.4
5.8
5.9
7
1.5
1.5
3.6
3.7
5.6
5.6
6.7
6.3
ns
6.6
All typical values are at VCC = 3.3 V, TA = 25
°
C.
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
相關(guān)PDF資料
PDF描述
SN54LVTH652JT Dual D-Type Flip-Flop with Set and Reset; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
SN54LVTH652W Dual D-Type Flip-Flop with Set and Reset; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
SN74LVTH652DGV 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
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