參數(shù)資料
型號(hào): SN54LVTH16835
廠商: Texas Instruments, Inc.
英文描述: Octal 3-State Inverting Buffer/Line Driver/Line Receiver; Package: SOIC-20 WB; No of Pins: 20; Container: Rail; Qty per Container: 38
中文描述: 的3.3V ABT生根粉18位通用總線驅(qū)動(dòng)3態(tài)輸出
文件頁(yè)數(shù): 6/8頁(yè)
文件大?。?/td> 121K
代理商: SN54LVTH16835
SN54LVTH16835, SN74LVTH16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVERS
WITH 3-STATE OUTPUTS
SCBS713C – MARCH 1998 – REVISED APRIL 1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH16835
VCC = 3.3 V
±
0.3 V
SN74LVTH16835
VCC = 3.3 V
±
0.3 V
VCC = 2.7 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
150
150
150
150
MHz
tw
Pulse duration
LE high
3.3
3.3
3.3
3.3
ns
CLK high or low
Data before CLK
3.3
3.3
3.3
3.3
2.2
2.5
2.1
2.4
tsu
Setup time
Data before LE
CLK high
2.5
1.7
2.3
1.5
ns
CLK low
1.5
0.5
1.5
0.5
th
Hold time
Data after CLK
Data after LE
1
0
1
0
ns
0.8
0.8
0.8
0.8
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH16835
SN74LVTH16835
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
±
0.3 V
VCC = 2.7 V
VCC = 3.3 V
±
0.3 V
TYP
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
150
150
150
150
MHz
A
Y
1.2
3.9
4.3
1.3
2.6
3.7
4
ns
1.2
3.9
4.3
1.3
2.4
3.7
4
LE
Y
1.4
5.3
5.9
1.5
3.2
5.1
5.7
ns
1.4
5.3
5.9
1.5
3.3
5.1
5.7
CLK
Y
1.4
5.3
5.9
1.5
3.5
5.1
5.7
ns
1.4
5.3
5.9
1.5
3.4
5.1
5.7
OE
Y
1.2
5
5.9
1.3
2.9
4.6
5.5
ns
1.2
5
5.9
1.3
3
4.6
5.5
OE
Y
1.6
1.6
6
6
6.5
6.5
1.7
1.7
4.2
3.7
5.8
5.8
6.3
6.3
ns
All typical values are at VCC = 3.3 V, TA = 25
°
C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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