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參數(shù)資料
| 型號： | SN54LVTH125J |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Quad Analog Switch/Multiplexer/Demultiplexer with Separate Analog and Digital Power Supplies; Package: SOIC 16 LEAD; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | 的3.3V ABT生根粉翻兩番總線緩沖器，具有三態(tài)輸出 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 413K |
| 代理商： | SN54LVTH125J |
SCBS703I AUGUST 1997 REVISED OCTOBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CC
)
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
I
off
and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
SN54LVTH125 . . . J OR W PACKAGE
SN74LVTH125 . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
SN54LVTH125 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1
1
N
3
3
V
4
2
G
N
C
NC No internal connection
SN74LVTH125 . . . RGY PACKAGE
(TOP VIEW)
1
14
7
8
2
3
4
5
6
13
12
11
10
9
4OE
4A
4Y
3OE
3A
1A
1Y
2OE
2A
2Y
1
3
V
G
description/ordering information
These bus buffers are designed specifically for low-voltage (3.3-V) V
CC
operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the
high-impedance state when the associated output-enable (OE) input is high.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN RGY
Tape and reel
SN74LVTH125RGYR
LXH125
SOIC D
Tube
SN74LVTH125D
LVTH125
Tape and reel
SN74LVTH125DR
40
°
C to 85
°
C
SOP NS
Tape and reel
SN74LVTH125NSR
LVTH125
SSOP DB
Tape and reel
SN74LVTH125DBR
LXH125
TSSOP PW
Tube
SN74LVTH125PW
LXH125
Tape and reel
SN74LVTH125PWR
TVSOP DGV
Tape and reel
SN74LVTH125DGVR
LXH125
CDIP J
Tube
SNJ54LVTH125J
SNJ54LVTH125J
55 C to 125 C
CFP W
Tube
SNJ54LVTH125W
SNJ54LVTH125W
LCCC FK
Tube
SNJ54LVTH125FK
SNJ54LVTH125FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74LVTH16244 | 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| SN74LVTH16244B | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 180pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: Sn60 Coated; Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate |
| SN74LVTH16244BDGG | 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| SN74LVTH16244BDGV | 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| SN74LVTH16244BDL | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 1800pF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: Sn60 Coated; Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: P Failure Rate |
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