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參數(shù)資料
| 型號(hào)： | SN54LVT543JT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
| 中文描述： | 的3.3V ABT生根粉八路收發(fā)登記，3態(tài)輸出 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 335K |
| 代理商： | SN54LVT543JT |
SN54LVT543, SN74LVT543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS137D – MAY 1992 – REVISED JULY 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static Power
Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CC
)
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
Support Live Insertion
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (JT) DIPs
description
These octal transceivers are designed specifically
for low-voltage (3.3-V) V
CC
operation, but with the
capability to provide a TTL interface to a 5-V
system environment.
The ’LVT543 contain two sets of D-type latches for
temporary storage of data flowing in either
direction. Separate latch-enable (LEAB or LEBA)
and output-enable (OEAB or OEBA) inputs are
provided for each register to permit independent
control in either direction of data flow.
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB
is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts
the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect
the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA,
LEBA, and OEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Copyright
1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
SN54LVT543 . . . JT PACKAGE
SN74LVT543 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LEBA
OEBA
A1
A2
A3
A4
A5
A6
A7
A8
CEAB
GND
V
CC
CEBA
B1
B2
B3
B4
B5
B6
B7
B8
LEAB
OEAB
SN54LVT543 . . . FK PACKAGE
(TOP VIEW)
3 2 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
B2
B3
B4
NC
B5
B6
B7
A2
A3
A4
NC
A5
A6
A7
4
26
14 15 16 17 18
A
C
G
N
O
L
B
A
O
L
N
C
B
V
C
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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| SN54LVT543 | 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
| SN74LVT543DWE4 | 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
| SN74LVT543DWR | 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
| SN74LVT543DWRE4 | 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
| SN74LVT543PW | 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
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