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參數(shù)資料
| 型號(hào)： | SN54LVT2952 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3V ABT Octal Bus Transceivers and Registers With 3-State Outputs(3.3V ABT 八總線收發(fā)器和寄存器(三態(tài)輸出)) |
| 中文描述： | 3.3生根粉八路總線收發(fā)器和寄存器具有三態(tài)輸出電壓（3.3V ABT生根粉八總線收發(fā)器和寄存器（三態(tài)輸出）） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 203K |
| 代理商： | SN54LVT2952 |
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B8
B7
B6
B5
B4
B3
B2
B1
OEAB
CLKAB
CLKENAB
GND
V
CC
A8
A7
A6
A5
A4
A3
A2
A1
OEBA
CLKBA
CLKENBA
SN54LVT2952 . . . JT PACKAGE
SN74LVT2952 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
C
C
G
N
C
C
O
B
N
A
V
B
B
A
C
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12 13 14 15 16 1718
5
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24
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A6
A5
A4
NC
A3
A2
A1
B5
B4
B3
NC
B2
B1
OEAB
4
26
SN54LVT2952 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
SN54LVT2952, SN74LVT2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS152E – MAY 1992 – REVISED JULY 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CC
)
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
Support Live Insertion
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (JT) DIPs
description
These octal bus transceivers and registers are
designed specifically for low-voltage (3.3-V) V
CC
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
The ’LVT2952 consist of two 8-bit back-to-back
registers that store data flowing in both directions
between two bidirectional buses. Data on the A or
B bus is stored in the registers on the low-to-high
transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input
is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT2952 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT2952 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74LVT2952 is characterized for operation from –40
°
C to 85
°
C.
Copyright
1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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