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參數(shù)資料
| 型號： | SN54LVC373AFK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Phase Locked Loop; Package: TSSOP-16; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | 八路透明D類鎖存器具有三態(tài)輸出 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 127K |
| 代理商： | SN54LVC373AFK |
SN54LVC373A, SN74LVC373A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS295J – JANUARY 1993 – REVISED JUNE 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Power Off Disables Outputs, Permitting
Live Insertion
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
CC
)
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and DIPs (J)
description
The SN54LVC373A octal transparent D-type latch
is designed for 2.7-V to 3.6-V V
CC
operation and
the SN74LVC373A octal transparent D-type latch
is designed for 1.65-V to 3.6-V V
CC
operation.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LVC373A is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74LVC373A is characterized for operation from –40
°
C to 85
°
C.
Copyright
1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
SN54LVC373A . . . J OR W PACKAGE
SN74LVC373A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
SN54LVC373A . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
2Q
3Q
3D
4D
1
1
O
5
5
8
4
G
L
V
C
8D
7D
7Q
6Q
6D
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54LVC373AJ | Phase Locked Loop; Package: SOEIAJ-16; No of Pins: 16; Container: Rail; Qty per Container: 50 |
| SN54LVC373AW | Phase Locked Loop; Package: SOEIAJ-16; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2000 |
| SN74LVC373ADB | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| SN54LVC541 | Analog Multiplexers/Demultiplexers; Package: SOIC 16 LEAD; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2500 |
| SN74LVC541ADB | OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54S00J | 制造商:Texas Instruments 功能描述:NAND Gate 4-Element 2-IN Bipolar 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54S00W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54S02J | 制造商:Texas Instruments 功能描述: |
| SN54S03J | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:2-INPUT NAND GATE (OC) - Rail/Tube |
| SN54S04J | 制造商:Texas Instruments 功能描述:Inverter 6-Element Bipolar 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:INVERTER 6-ELEM BIPOLAR 14CDIP - Rail/Tube 制造商:Texas Instruments 功能描述:HEX INVERTER *NIC* |
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