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參數(shù)資料
| 型號： | SN54LV595AJ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal D-Type Flip-Flop; Package: 20 LEAD PDIP; No of Pins: 20; Container: Rail; Qty per Container: 18 |
| 中文描述： | 8位移位寄存器3態(tài)輸出寄存器 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 492K |
| 代理商： | SN54LV595AJ |
SCLS414N APRIL 1998 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.
The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage
register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output
for cascading. When the output-enable (OE) input is high, all outputs except Q
H
′
are in the high-impedance
state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
FUNCTION
SER
SRCLK
SRCLR
RCLK
OE
X
X
X
X
H
Outputs QAQH are disabled.
Outputs QAQH are enabled.
Shift register is cleared.
X
X
X
X
L
X
X
L
X
X
L
↑
H
X
X
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X
X
X
↑
X
Shift-register data is stored in the storage register.
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