參數(shù)資料
型號: SN54LV540A
廠商: Texas Instruments, Inc.
英文描述: Quad OR Gate; Package: TSSOP-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2500
中文描述: 八路緩沖器/ 3司機態(tài)輸出
文件頁數(shù): 1/7頁
文件大?。?/td> 130K
代理商: SN54LV540A
SN54LV540A, SN74LV540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS409B – APRIL 1998 – REVISED NOVEMBER 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic
Small-Outline (DW, NS), Shrink
Small-Outline (DB), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Packages, Chip
Carriers (FK), and DIPs (J)
description
The ’LV540A devices are octal buffers/drivers
designed for 2-V to 5.5-V V
CC
operation.
These devices are ideal for driving bus lines or
buffer memory address registers. They feature
inputs and outputs on opposite sides of the
package to facilitate printed circuit board layout.
The 3-state control gate is a two-input AND gate
with active-low inputs so that if either
output-enable (OE1 or OE2) input is high, all
corresponding outputs are in the high-impedance
state. The outputs provide inverted data when
they are not in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LV540A is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74LV540A is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each buffer/driver)
INPUTS
OE2
OUTPUT
Y
OE1
A
L
L
L
H
L
L
H
L
H
X
X
Z
X
H
X
Z
Copyright
1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SN54LV540A . . . J OR W PACKAGE
SN74LV540A . . . DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Y1
Y2
Y3
Y4
Y5
A3
A4
A5
A6
A7
SN54LV540A . . . FK PACKAGE
(TOP VIEW)
A
A
O
Y
Y
O
A
G
Y
V
C
相關(guān)PDF資料
PDF描述
SN54LV540AFK Quad OR Gate; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
SN54LV540AJ Quad OR Gate; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
SN54LV540AW Quad OR Gate; Package: PDIP-14; No of Pins: 14; Container: Rail; Qty per Container: 500
SN74LV573AGQNR Circular Connector; No. of Contacts:11; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:19; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:19-11 RoHS Compliant: No
SN74LV573ADB OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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